HR1001C Enhanced LLC Controller SOIC
HR1001C Enhanced LLC Controller SOIC

HR1001C Enhanced LLC Controller SOIC

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pMPS HR1001C — Enhanced LLC Controller, SOIC./p
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    HR1001C Enhanced LLC Controller SOIC

    The MPS HR1001C is a Enhanced LLC Controller. It is supplied in a SOIC package.

    The HR1001C is an enhanced LLC controller that provides adaptive dead-time adjustment (ADTA) and capacitive mode protection (CMP) features, as well as functional improvements on surge performance.

    Key Specifications

    Part NumberHR1001C
    FunctionEnhanced LLC Controller
    PackageSOIC
    Ordering CodesHR1001C

    Features

    • Over-Current Protection (OCP) with Programmable Delay for Enhanced Surge Performance
    • Adaptive Dead-Time Adjustment (ADTA)
    • Capacitive Mode Protection (CMP)
    • 50% Duty Cycle, Variable Frequency Control for Resonant Half-Bridge Converter
    • 600V High-Side Gate Driver with Integrated Bootstrap Diode with a High-Accuracy Oscillator of High dV/dt Immunity
    • Operates up to 600kHz
    • Two-Level Over-Current Protection (OCP): Frequency Shift and Latched Shutdown with Programmable Duration Time
    • Latched Disable Input for Easy Protection
    • Remote On/Off Control and Brown-Out Protection through BO
    • Programmable Burst Mode Operation at Light Load

    Typical Application Circuit

    HR1001C typical application circuit
    HR1001C typical application circuit, as published in the MPS datasheet.

    Applications

    • LCD and PDP TVs
    • Desktop PCs and Servers
    • Telecom SMPS
    • AC/DC Adapter, Open-Frame SMPS
    • Video Game Consoles

    Design Notes

    • The PFC inductor must support the maximum duty cycle at the lowest line voltage, which is where saturation risk peaks.
    • High-voltage startup and X-capacitor discharge paths dominate no-load standby loss; verify them against the efficiency target.
    • Leakage inductance and the RCD clamp set the turn-off loss — snubber values are a thermal trade-off, not a fixed recipe.
    • Synchronous rectification timing must track the primary switching; a mistimed SR FET conducts through its body diode and fails hot.

    Common Questions

    Which package and ordering codes apply to the HR1001C?
    SOIC; order codes include HR1001C.
    What are the defining features of the HR1001C?
    Over-Current Protection (OCP) with Programmable Delay for Enhanced Surge Performance Adaptive Dead-Time Adjustment (ADTA)

    Shenzhen Gaorunxin Technology Co., Ltd

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