HR1002A Enhanced LLC Controller SOIC16
HR1002A Enhanced LLC Controller SOIC16

HR1002A Enhanced LLC Controller SOIC16

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pMPS HR1002A — Enhanced LLC Controller, SOIC16./p
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    HR1002A Enhanced LLC Controller SOIC16

    The MPS HR1002A is a Enhanced LLC Controller. It is supplied in a SOIC16 package.

    The HR1002A is an enhanced LLC controller that provides robust adaptive dead-time adjustment (ADTA) and capacitive mode protection (CMP), as well as improved functional surge performance.

    Key Specifications

    Part NumberHR1002A
    FunctionEnhanced LLC Controller
    PackageSOIC16
    Ordering CodesHR1002A

    Features

    • Over-Current Protection (OCP) with Configurable Delay for Enhanced Surge Performance
    • Adaptive Dead-Time Adjustment (ADTA)
    • Capacitive Mode Protection (CMP)
    • 50% Duty Cycle, Variable Frequency Control for Resonant Half-Bridge Converter
    • 600V High-Side Gate Driver with Integrated Bootstrap Diode, High-Accuracy Oscillator, and High dV/dt Immunity
    • Operates Up to 600kHz
    • Two-Level Over-Current Protection (OCP): Frequency Shift and Latched Shutdown with Configurable Duration
    • Latched Disable Input for Easy Protection
    • Remote On/Off Control and Brownout Protection through BO
    • Configurable Burst Mode Operation under Light-Load Conditions

    Typical Application Circuit

    HR1002A typical application circuit
    HR1002A typical application circuit, as published in the MPS datasheet.

    Applications

    • LCD and PDP TVs
    • Desktop PCs and Servers
    • Telecom SMPSs
    • AC/DC Adapters, Open-Frame SMPSs
    • Power Tools
    • Video Game Consoles

    Design Notes

    • The PFC inductor must support the maximum duty cycle at the lowest line voltage, which is where saturation risk peaks.
    • High-voltage startup and X-capacitor discharge paths dominate no-load standby loss; verify them against the efficiency target.
    • Leakage inductance and the RCD clamp set the turn-off loss — snubber values are a thermal trade-off, not a fixed recipe.
    • Synchronous rectification timing must track the primary switching; a mistimed SR FET conducts through its body diode and fails hot.

    Common Questions

    Which package and ordering codes apply to the HR1002A?
    SOIC16; order codes include HR1002A.
    What are the defining features of the HR1002A?
    Over-Current Protection (OCP) with Configurable Delay for Enhanced Surge Performance Adaptive Dead-Time Adjustment (ADTA)

    Shenzhen Gaorunxin Technology Co., Ltd

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    Shenzhen Gaorunxin Technology Co., Ltd

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