MP20075 1.05-3.6V 3A, 1.05V–3.6V DDR2/3/3L/4 Memory Termination Regulator MSOP8

MP20075 1.05-3.6V 3A, 1.05V–3.6V DDR2/3/3L/4 Memory Termination Regulator MSOP8

The MP20075 precision DDR2/3/3L/4 termination LDO regulator features a precision VREF/2 tracking voltage for accurate termination.

Key Specifications

Features

• VDDQ Voltage Range: 1.05V to 3.6 V
• Up to 3A Integrated Sink/Source Linear Regulator with Accurate VREF/2 Divider Reference for DDR2/3/3L/4 Termination
• Requires Only 20μF Ceramic Output Capacitance
• Drive Voltage: 3.3V
• 1.05V Input (VDDQ) Helps Reduce Total Power Dissipation
• Integrated Divider Tracks VREF for accurate VTT and VTTREF Output Voltage
• Kelvin Sensing (VTTSEN)
• ±30mV Accuracy for VTT
• ±18mV Accuracy for VTTREF
• Built-In Soft-Start, UVLO and OCL

Typical Application Circuit

Applications

• Notebook DDR2/3/3L/4 Memory Supply and Termination Voltage in ACPI Compliant Systems

Design Notes

• Dissipation is (VIN − VOUT) × IOUT. Check it against the package thermal resistance at the real ambient temperature before committing to the full rated current.
• Some low-noise LDOs require a minimum output capacitor ESR for loop stability — read the stability section before substituting a ceramic part.
• Add a bypass capacitor on the reference pin where provided; it sets the output noise floor.
• PSRR falls as the input-to-output differential shrinks, so headroom matters at low VIN.

Common Questions